One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND. This was one of numerous innovations the company’s EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.
The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there. Samsung seems to have a policy that prohibits sharing such presentations.
Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel! The result is the graphic for this blog post. The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND. You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.
Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago. This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”
The single most interesting thing I learned at the 2015 Flash Memory Summit was that 3D NAND doesn’t have a natural limit, after which some other memory type will need to be adopted.
For years SanDisk has been presenting a memory roadmap (this post’s graphic is one rendition) that anticipates a move to ReRAM after 3D NAND has run through its natural life, which was expected to be as little as three generations. This has been backed by the idea that a 3D NAND stack would only be able to reach a certain number of layers before it would encounter difficulties caused by the need to etch a high aspect ratio hole through an increasing number of layers.
The aspect ratio issue is not hard to understand: Let’s assume that the hole in a 24-layer stack has an aspect ratio of 40:1, then a 32-layer hole would have an aspect ratio of about 50:1, and a 64-layer stack would be something close to 100:1. Today’s technology starts to have trouble etching holes with an aspect ratio higher than 60:1.
These high aspect ratios were thought to be the limiting factor that would prevent 3D NAND from continuing for more than three generations. 3D NAND could only have as many layers as the aspect ratio could support.
On a panel that I moderated at this year’s Flash Memory Summit one panelist, Dr. Myoung Kwan Cho of SK hynix, explained that although there is a limit Continue reading “Flash Memory Summit: Limitless Layers of 3D NAND”
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
In its summer 2013 V-NAND announcement, Samsung explained that it would be Continue reading “3D NAND’s Impact on the Equipment Market”
Early this month I was invited to participate in Applied Materials’ (AMAT) Analyst Day. The sessions were rich in data covering the markets that would profit the company over the next few years.
Naturally, The Memory Guy fixated on those presentations that dealt with memory. When it came to the upcoming transition to 3D NAND, AMAT had a lot to say.
A later post will explain what 3D NAND actually is. Suffice it to say that today’s approach to making NAND flash has nearly reached its limit, and the approach that manufacturers plan to use in the future involves making NAND strings that stand on their ends. This has phenomenal implications on Continue reading “Applied’s Take on 3D NAND”