Intel

Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane

Ron NealeThis is Part 4 of a series in the Memory Guy blog, which has been looking at some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.  I want, in this final part, to focus on its possible implications for commercial PCM products.


When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM).  Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.

The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs.  In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance.  (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)

As the calculated Continue reading

Ron Neale To Share Posts

Ron NealeThe Memory Guy is pleased to begin publishing posts from Ron Neale.  Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.

Ron’s career has centered around phase-change memory.  He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.

Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.

Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.

Original PCM Article from 1970

For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device.  After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.

The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron).  Intel, though, didn’t appear to have anything to share but the cover photo.

Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.

It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who is a regular contributor to EE Times.

I was astounded to discover that Continue reading

Micron and Intel to End NAND Flash JV

Jim Handy in the IMFT fabIt came as a surprise to the Memory Guy on Monday to receive a press release from Micron indicating that Intel and Micron had decided to end their NAND flash partnership.

This agreement, which was begun in 2006, helped the two companies to aggressively ramp into the NAND flash market by combining their resources.  NAND flash makers (as well as DRAM makers) need to make very substantial capital investments to participate in the market, and that’s not easy for a new entrant.  Micron at that time was a very small NAND flash maker, and Intel wasn’t involved in the NAND flash market at all, so neither was in a position to succeed.  By combining their resources the companies were able to become important contributors to the market.

The agreement initially appeared to be modeled after the very successful joint venture that Toshiba and SanDisk enjoyed.  Each company would contribute half of the JV’s capital investment, and the same designs would be used to make both companies’ chips.

Over time Intel found itself in a familiar Continue reading

3D NAND: “I Have More Layers than You Do!”

Layer CountYesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.

Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”

The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.

The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time.  By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).

WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers.  The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.

One has to wonder if WDC was Continue reading

Is Intel Adding Yet Another Memory Layer?

Where the Piecemakers DRAM FitsAt the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.

The chip was designed with a focus on latency, rather than bandwidth.  This is unusual for a DRAM.

Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).  Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels.  The researchers decided to design a product to fill this gap.

Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory.  The gap that needs filling is Continue reading

Samsung Power Glitch – Is It Important?

3D NANDOn Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure.  How much of a problem is this?

The answer really depends upon who you ask.  An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days.  The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.

Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.

Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal.  It won’t make heavy impact on Samsung’s chip business and the entire industry.”

According to Korean news source Chosenilbo the outage was caused by Continue reading

IBM Jumps on the “New Memory” Bandwagon

IBM's 3-Bit PCM Read AlgorithmAt a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM).  The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.

Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.

With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory.  Such a layer would improve the cost/performance of all types of Continue reading

New Report: 3D XPoint Memory

3D XPoint Report Graphic

Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.

The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology.  The report explains the technology and its special manufacturing challenges.  It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.

Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios.  Particular attention has been paid to its impact upon the DRAM, SSD, and other markets.  Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.

The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.

This breakthrough report is based on Continue reading

What Memory Will Intel’s Purley Platform Use?

Part of Intel Purley SlideThere has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap.  Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family.  (A review of this post on 7/13/17 revealed that The Platform’s website has disappeared.  The above link and the next one no longer work.)

One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”

The Memory Guy puzzled a bit about what this might be.  The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that.  MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.

Since that’s the case, then what is this mystery memory?  If we think of Continue reading