With the release of its Cascade Lake family of processors today (formally called the “2nd Generation Intel Xeon Scalable processor”) Intel disclosed more details about its Optane DIMM, which has been officially named the “Intel Optane DC Persistent Memory.” This DIMM’s architecture is surprisingly similar to an SSD, even to the point of its having error correction and encryption!
The Memory Guy doesn’t generally cover SSDs, but I do cover DIMMs, so this is one of those posts that I could have put into either of my blogs: The Memory Guy or The SSD Guy. I have decided to put it here with the hopes that it will be easier for members of the memory community to find.
The internal error correction, the encryption, and the fact that 3D XPoint Memory wears out and must use wear leveling, all cause the Optane DIMM’s critical timing path to be slower than the critical path in a DRAM DIMM, rendering the Optane DIMM unsuitable for code execution. This, and the fact that XPoint writes are slower than its reads, all help to explain why an Optane DIMM is never used as the only memory in a system: there is always a DRAM alongside the Optane DIMM to provide faster Continue reading “What’s Inside an Optane DIMM?”
For more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.
First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory. Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019. My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.
The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.
Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM. This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”
It’s earnings call season, and we have heard of a slowing DRAM market and NAND flash price declines from Micron, SK hynix, Intel, and now Samsung. DRAM prices have stopped increasing, and that can be viewed as a precursor to a price decline.
Samsung’s 31 October, 2018 3Q18 earnings call vindicated Objective Analysis‘ forecast for a 2H18 downturn in memories that will take the rest of the semiconductor market with it.
Those familiar with our forecast know that for a few years we have been predicting a downturn in the second half of this year as NAND flash prices fall, followed by a DRAM price collapse. After the DRAM collapse the rest of the semiconductor market will undergo a downturn.
We’ve been calling for this downturn for some time. Dan Hutcheson at VLSI Research has been videotaping our forecast every December for the past Continue reading “Memory Market Falling, as Predicted”
This is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.
I want, in this final part, to focus on its possible implications for commercial PCM products.
When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM). Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.
The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs. In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance. (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)
As the calculated Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane”
The Memory Guy is pleased to begin publishing posts from Ron Neale. Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.
Ron’s career has centered around phase-change memory. He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.
Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.
Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.
For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device. After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.
The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron). Intel, though, didn’t appear to have anything to share but the cover photo.
Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.
It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who has been a regular contributor to EE Times and who now also contributes blog posts to The Memory Guy.
I was astounded to discover that Continue reading “Original PCM Article from 1970”
It came as a surprise to the Memory Guy on Monday to receive a press release from Micron indicating that Intel and Micron had decided to end their NAND flash partnership.
This agreement, which was begun in 2006, helped the two companies to aggressively ramp into the NAND flash market by combining their resources. NAND flash makers (as well as DRAM makers) need to make very substantial capital investments to participate in the market, and that’s not easy for a new entrant. Micron at that time was a very small NAND flash maker, and Intel wasn’t involved in the NAND flash market at all, so neither was in a position to succeed. By combining their resources the companies were able to become important contributors to the market.
The agreement initially appeared to be modeled after the very successful joint venture that Toshiba and SanDisk enjoyed. Each company would contribute half of the JV’s capital investment, and the same designs would be used to make both companies’ chips.
Over time Intel found itself in a familiar Continue reading “Micron and Intel to End NAND Flash JV”
Yesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””
At the International Solid State Circuits Conference (ISSCC) last week a new “Last Level Cache” was introduced by a DRAM company called “Piecemakers Technology,” along with Taiwan’s ITRI, and Intel.
The chip was designed with a focus on latency, rather than bandwidth. This is unusual for a DRAM.
Presenter Tah-Kang Joseph Ting explained that, although successive generations of DDR interfaces has increased DRAM sequential bandwidth by a couple of orders of magnitude, latency has been stuck at 30ns, and it hasn’t improved with the WideIO interface or the new TSV-based High Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC). Furthermore, there’s a much larger latency gap between the processor’s internal Level 3 cache and the system DRAM than there is between any adjacent cache levels. The researchers decided to design a product to fill this gap.
Many readers may be familiar with my bandwidth vs. cost chart that the Memory Guy has used to introduce SSDs and 3D XPoint memory. The gap that needs filling is Continue reading “Is Intel Adding Yet Another Memory Layer?”
On Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure. How much of a problem is this?
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”
According to Korean news source Chosenilbo the outage was caused by Continue reading “Samsung Power Glitch – Is It Important?”