One of the more fun aspects of last week’s Flash Memory Summit was the presentation of the Lifetime Achievement Award. This is something that the show’s management has allowed me to do for the past four events.
This year’s award went to Dr. Simon Sze, who co-invented the floating gate transistor (the basis for all flash, EEPROM, and EPROM) at Bell Labs back in 1967.
Sze and his partner Dawon Kahng were finishing lunch in the company cafeteria with a cheesecake dessert. The two discussed what would happen if a MOSFET was built with extra layers like the layers in the cake. Their intent was to use semiconductors to replace Continue reading “Cheesecake and Floating Gates”
This series has looked at 3D NAND technology in a good deal of technical depth. The last question to be answered centers around the players and the timing of the technology. A lot has been said about the technology and its necessity. Will everyone be making 3D NAND? When will this big transition occur?
This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding. Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.
Let’s start with Samsung, the largest producer of NAND flash today. Just prior to Memcon 2013 last Continue reading “3D NAND: Who Will Make It and When?”
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.
Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!
Part of this stems from the use of a different kind of NAND bit cell. You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading “An Alternative Kind of Vertical 3D NAND String”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”