In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”
Ron Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.
At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”. It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”
Readers who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook. In this post I will share some key elements of our emerging memory forecast.
Since this is a simple blog post the forecast coverage is brief. The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.
The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.) Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications. The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.
At tighter processes flashless versions of some MCUs already ship that can Continue reading “Emerging Memories Today: Forecasting Emerging Memories”
Most memory industry participants view emerging memories as the eventual path of the business: There’s no doubt that today’s memory technologies will stop scaling, and that new memory technologies will need to replace today’s leading technologies both in the embedded and stand-alone spaces. This includes DRAM, NAND flash, NOR flash, and SRAM. Because this outlook is held by nearly everyone in the industry, all major memory manufacturers are investing in alternative memory technologies. The leading players are researching multiple technologies at the same time.
Meanwhile, the industry outlook has allowed many university research projects and other similar efforts to gain funding to develop new memory types, spawning a large number of small single-technology companies tightly focused on one technology or another: ReRAM, MRAM, FRAM, and others, including such highly-differentiated technologies as carbon nanotubes and printable polymers.
In our Emerging Memory report Tom Coughlin and I did our Continue reading “Emerging Memories Today: Emerging Memory Companies”
Something that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field. This is not measured in pages, but in the topics that we cover. For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.
All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common. One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)
This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others. For the most part these tools will be used for deposition and etch. The lithography requirements will be satisfied by the tools used to pattern the metal layers.
The process flow in this figure sheds some light on the steps that Continue reading “Emerging Memories Today: Process Equipment Requirements”
Here in the US we use an extremely odd expression. If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!” This is a very lengthy way to say: “numerous.” (I don’t believe that ANYONE understands how that expression became a part of our vernacular!) Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today. There are certainly lots of them!
This post is intended to be very high-level technical description of today’s leading emerging memory technologies. These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.
PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures. The crystalline state has a low resistance and the amorphous state has a high resistance. This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.
In chemistry and physics, anything with a Continue reading “Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.”
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves. The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology. Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!
A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here. It’s not complicated.
Every bit cell in a memory chip requires a selector. This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written. The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading “Emerging Memories Today: Understanding Bit Selectors”
Non-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred. Why is that, and why should anything change?
This is a question that The Memory Guy is often asked. The answer is relatively simple.
Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes. In fact, before the middle 1980s, logic and memory processes were identical. It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.
Even so, memory processes and logic processes are more similar than different. This synergy between memory and logic continues to reduce the process development cost for both memories and logic.
Emerging memories depart from Continue reading “Emerging Memories Today: Why Emerging Memories are Necessary”
There’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own. Today it appears that their opportunity is very near.
Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue. But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies. Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing. It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.
This post introduces a Continue reading “Emerging Memories Today: New Blog Series”
This is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.
After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.
In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper. This means that, Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation”