What really happens in NAND flash during an MLC, TLC, or QLC write? Although there are lots of websites that explain that multilevel cells store four, or eight, or sixteen different voltage levels on a cell (for MLC, TLC, or QLC), they don’t spell out the process of putting those voltage levels onto the bit cell.
Fortunately, Vic Ye, Manager, NAND Flash Characterization at Yeestor Microelectronics Co., Ltd. in Shenzhen, China presented the programming process in a series of short videos at the Flash Memory Summit last August. The Memory Guy was fortunate enough to attend his presentation. Yeestor is a fabless semiconductor manufacturer that manufactures flash storage controllers for SSDs (PCIe & SATA) and flash cards (SD, UFS, eMMC, etc.)
Mr. Ye later gave me permission to share his videos and these are the foundation of this post. They’re brief (13 seconds to 1:10) so they won’t take much time to review. The videos were a part of his slide presentation titled: A Graphical Journey into 3D NAND Program Operations that can be downloaded from The Flash Memory Summit website by clicking the presentation title above and entering your e-mail address.
A multilevel flash bit cell has Continue reading “Videos Demystify MLC NAND Programming”
Error Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years. The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!
Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies? The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often. This technique has been used for a long time in both communications channels and in hard disk drives. Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data. Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right. These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today is a very well-developed science.
Denali Software published a nice Continue reading “How 3D NAND Shrinks ECC Requirements”
Yesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””
At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading “IBM Jumps on the “New Memory” Bandwagon”
An article in a recent issue of Business Korea posits that Apple may be having trouble stemming from the company’s adoption of TLC flash in it’s new iPhone 6.
The article states:
considering that technical defects mainly occur in the 128GB version of the iPhone 6 Plus, there might be a problem in the controller IC of triple-level cell (TLC) NAND flash.
The problem has led to numerous warranty replacements and the looming prospects of a recall.
(Note that Continue reading “Is Apple Losing Dollars to Save a Few Cents?”
Samsung has finally introduced the 3-bit 3D NAND chip it revealed at last August’s Flash Memory Summit. This announcement was made in the form of an SSD announcement.
For those who were unable to attend the Flash Memory Summit, Samsung’s Senior VP of Memory R&D, Bob Brennan, announced in his keynote speech that a 3D 32-layer V-NAND, a chip that would achieve twice the chip density of planar NAND, was entering production and that SSDs would follow in a month. Now, two months later, Samsung has announced those SSDs.
This week’s release reiterates Continue reading “Finally! Samsung’s 3-Bit V-NAND Arrives”
From time to time I get questions from investors in the memory business asking: “What is a multilayer cell?”
The answer is: “There is no such thing: It’s a misstatement.”
The term “MLC” has, by a number of people, been mistranslated to “multi-layer cell.” The misunderstanding appears to have originated in the financial community. People in the flash memory business never use the term at all.
Yes, we talk about MLC, but to us the term means “multilevel cell”.
A multilevel cell is a cell that uses varying voltage levels to represent different states. With four voltage levels the resulting four states on a single cell can be turned into Continue reading “What is a “Multilayer Cell”?”
DensBits, an Israeli start-up, has introduced a new technology and a new product today. The company’s new eMMC controller, the DB3610, embodies DensBits’ “Memory Modem” technology, which is a blend of ECC, DSP, and flash management that the company says can give TLC flash endurance superior to that of MLC flash with performance nearly as good as competing controllers can provide with MLC.
That’s a big claim!
DensBits’ Memory Modem views NAND flash as a noisy communications channel, using those algorithms developed to support deep Continue reading “DensBits – Making TLC Act Like MLC”
One memory chip was so important that it was presented three times at this week’s International Solid State Circuits Conference (ISSCC) and that was the Toshiba/SanDisk 128Gb NAND flash. This chip was shown by Eli Harari in Monday’s keynote, then was featured twice in the Wednesday afternoon Nonvolatile Memories session – once by Toshiba and once by SanDisk.
The NAND chip, measuring 170.6mm², is said by both companies to be the densest NAND available. Compared to the Intel/Micron 64Gb 20nm NAND at 118mm², the device gives twice the bits in a 45% larger die area, so the companies’ claim rings true, since the only other NAND makers: Samsung and Hynix, have processes that fall far behind at 27nm and 26nm respectively.
Continue reading “Inside SanDisk’s & Toshiba’s New 128Gb NAND Chip”