Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane

Ron NealeThis is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.

I want, in this final part, to focus on its possible implications for commercial PCM products.

When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM).  Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.

The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs.  In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance.  (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)

As the calculated cell endurance of the latest commercially-available PCM devices towards the bottom of the table appear to provide no improvement over earlier versions, will a significant improvement in endurance ever be possible for 3DXPoint and Optane without switching to the bipolar operation described in Part 3 and converting the cell to one based on ALD deposited nano-crystal GST and a tapered pore structure as described in Part 1?

Endurance of Optane SSDs

To explain the format of the table, the white cells contain figures that are sourced either from Intel specifications, or, when these are unavailable, from articles from reputable sources.  All of the yellow cells are calculated.  This  was done to allow readers to compare similar specifications since Intel specifies different drives using different measures.  (The math behind these calculations appears in yet another SSD Guy blog post.)

While a tapered cell would not be impossible in a stacked memory array, it would be a significant challenge, even more challenging will be the filling of high aspect ratio pores with nano-crystal GST ALD across large silicon wafers.

The stacked arrays of other emerging memory technologies have a mandatory requirement for bipolar operation in order to achieve the two memory states.  A positive current is used to set a bit, and a reverse current is used to clear it.  If these arrays are to eventually be constructed in stacked form the requirement for a thin film, bidirectional, high switching endurance matrix isolation device will become essential, irrespective of its use in PCM arrays.

Perhaps arsenic-doped GST will provide that answer. If not, then a level of understanding of element separation equal to that derived from the IBM/Yale work on PCM must be obtained and applied to any of the candidate thin-film threshold switches. (Graduate students get to work -riches await the successful)

For Intel there might be some good news, provided that the threshold switch is not the weak link in each of their Optane memory cell chains and if Intel have really developed a truly solid state electronic switching, high reliability bidirectional threshold switch for their matrix isolation device.

If so, they will hold the key to the future development in the direction of stacked arrays not only for a number of other emerging memory technologies where bipolar operation is mandatory, but also for other possible switching and logic applications for that device.

Only Intel can tell us, that is if they really know, what is the real cause is of the poor endurance of their 3D XPoint-based Optane products and what seems to be their inability to do much about it for each generation of their products.

It is possible that Intel’s PCM endurance is related to some identifiable fabrication defect/process yield problem and might be solved with the steady evolution of their fabrication processes.

On a personal basis all I can say is that the home-built family computer with a Intel Optane Memory 32GB M.2 HDD Accelerator has, so far, (months) shown no sign of any reliability or operational problems and fires up each morning ready with our most often used applications.

One thought on “Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane”

  1. It is interesting to measure the writes to memory for the most used applications that are running on top of Optane in your home-built computer. Many server applications write heavily to memory. The reasons are versatile. Intel’s PCM counter facility makes it very easy to monitor write traffic to memory.

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