At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material. This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.
For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.
imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.” Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation. The device’s characteristics are shown in this post’s graphic.
The consortium reports that the current through the Continue reading “New Materials Solve Key 3D NAND Issue”
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.
For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.
The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.
These papers are organized into Continue reading “New Book: Vertical 3D Memory Technologies”
Samsung has announced that the company’s newest memory fabrication plant (Fab) in Xi’an, China has “begun full-scale production operations”, adding that: “The new facility will manufacture Samsung’s advanced NAND flash memory chips: 3D V-NAND.”
I immediately asked whether the plant will build products other than 3D NAND, and the company has replied that this will be the only product produced in the Xi’an plant. What Samsung has not said is what is meant by “full-scale production operations.” Typically wafer fabs start with a very low production capacity as new tools are being qualified, only ramping to high-volume production a year or more after initial production.
Samsung points out that production has begun a mere 20 months after initial groundbreaking, which is quite Continue reading “Samsung Begins Operations at its Xi’an Fab”
This series has looked at 3D NAND technology in a good deal of technical depth. The last question to be answered centers around the players and the timing of the technology. A lot has been said about the technology and its necessity. Will everyone be making 3D NAND? When will this big transition occur?
This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding. Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.
Let’s start with Samsung, the largest producer of NAND flash today. Just prior to Memcon 2013 last Continue reading “3D NAND: Who Will Make It and When?”
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
In its summer 2013 V-NAND announcement, Samsung explained that it would be Continue reading “3D NAND’s Impact on the Equipment Market”
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?”
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have determined to take this route. Why is that?
In Spansion’s case, a charge trap was a means of doubling the bit capacity of its products. It was an inexpensive alternative to standard MLC flash. To date this strategy has worked very well.
As mentioned in that earlier post, 3D NAND uses a charge trap because it’s extremely difficult to create features, like a floating gate, sideways – lithography works from the top down. A charge trap, when used to replace a floating gate, doesn’t need to be patterned, since the Continue reading “3D NAND: Benefits of Charge Traps over Floating Gates”
One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array. Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.
The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below. Instead you have to create a terrace structure to expose and connect to each layer.
These connections are made by etching a stair-step pattern into the layers and sinking Continue reading “3D NAND: How do You Access the Control Gates?”
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not be scaled much farther in length and width on the die’s surface. Toshiba invented a 3D NAND which has been adopted and refined by all flash makers. The idea is simple: Rather than shrink the cell’s length and width, why not turn the NAND string so that it’s standing on its end?
This concept is illustrated by this post’s first graphic, which was provided by Applied Materials. (Click on the graphic to see the whole thing at a larger size.) A standard NAND string that normally runs longitudinally is turned on its end to become a vertical string. Not only that, but it makes things easier if the string is split into two sections and Continue reading “What is a 3D NAND?”
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost importance in the world of memory.
Memory chip makers have shrunk the cost of a bit some nine orders of magnitude since the 1960s largely by shrinking the process, or “scaling” to increasingly tighter process geometries.
Flash has always been expected to reach a scaling limit. Over the past few generations technologists have developed Continue reading “Why Do We Need 3D NAND?”