There has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap. Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family. (A review of this post on 7/13/17 revealed that The Platform’s website has disappeared. The above link and the next one no longer work.)
One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”
The Memory Guy puzzled a bit about what this might be. The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that. MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.
Since that’s the case, then what is this mystery memory? If we think of Continue reading “What Memory Will Intel’s Purley Platform Use?”
Everspin and Northwest Logic have just announced full interoperability between Northwest Logic’s MRAM Controller Core and Everspin Technologies’ ST-MRAM (Spin-Torque Magnetic RAM) chips. This interoperability is hardware proven on a Xilinx Virtex-7 FPGA and is now available for designs needing low-latency, high memory throughput using MRAM technology.
Since The Memory Guy knew that Everspin’s EMD3D064M ST-MRAM was fully DDR3 compatible, I had to wonder why the part would require a special controller – couldn’t it simply be controlled by any DDR3 controller?
Everspin’s product marketing director, Joe O’Hare, took the time to Continue reading “Why ST-MRAMs Need Specialized DDR3 Controllers”
The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”
Wiley has recently published a new book by Betty Prince titled Vertical 3D NAND Technologies that is one to consider if you want to bring yourself up to speed on recent research behind today’s and tomorrow’s 3D memory technologies.
For those who haven’t previously encountered Dr. Prince, she is the author of a number of key books covering memory design and holds memory patents written over her 30-year career in the field.
The book provides capsule summaries of over 360 papers and articles from scholarly journals on the subject of 3D memories, including DRAM, NAND flash, and stacked chips.
These papers are organized into Continue reading “New Book: Vertical 3D Memory Technologies”
Some time ago The Memory Guy was asked by Numonyx (later acquired by Micron) to put together an online course for EE Times on memory technologies, explaining how each one works and where it is used.
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading “Fundamentals of Memory – Free Online Course”
The December issue of the IEEE Spectrum includes a fascinating article about a 100 million cycle flash memory developed by Macronix. The company will present this design at at IEDM this month.
In brief: Macronix’ researchers buried a heater in the array to heat the tunnel dielectric, annealing out the disruptions & traps that might cause a bit to fail.
A prototype has so far been tested more than 100 million cycles and it shows no sign of impending failure. Researchers believe that it is likely to reach one billion or more cycles, but such testing will take several months. This just may be able to Continue reading “Macronix Solves Flash Wear Problem”
Everspin today announced that select customers have been sampled the world’s first “ST-RAM” a 64Mb chip using STT MRAM technology, rather than Everspin’s existing production toggle MRAM technology.
For the past decade or so memory researchers have been looking to Spin Transfer Torque (sometimes called “Spin Torque Transfer”) MRAMs as a way of getting to tighter processes than conventional toggle MRAM. It seems that current densities in toggle MRAM rise too high as the process shrinks – at some point the process could no longer scale since chips would burn themselves out during programming. The ST-RAM paves Everspin’s path toward Continue reading “Everspin Samples First STT MRAM”
Lane Mason of Objective Analysis recently shared with The Memory Guy an article he wrote for the 4 April 2007 Denali Memory Report covering Phase Change Memory (PCM or PRAM.) It looked like something big was about to happen with the technology: PCM looked nearly ready to enter production.
The article included an excerpt of an EE Times interview with Micron’s CEO, the late Steve Appleton, in which Appleton stated that PCM advocates threatened to take over the memory market in 2000.
Here it is 2012, and PCM represents little more than a drop in the bucket when it comes to memory sales, although Continue reading “Alternative Memory Technologies Patiently Wait For Market to Explode”
Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading “The End of Flash Scaling”