3DNAND - The Memory Guy Blog

3D NAND: Who Will Make It and When?

(The following is an update of a post that originally ran on 13 December 2013. It was republished in 2024 as a part of a series on The Memory Guy blog to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

This series, originally run in 2013, has looked at 3D NAND technology in a good deal of technical depth. At that time, the last question to be answered centered around the players and the timing that the technology would Continue reading “3D NAND: Who Will Make It and When?”

3D NAND’s Impact on the Equipment Market

(The following is an update of a post that originally ran on 6 December 2013. It was republished in 2024 as a part of a series on The Memory Guy blog to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

A very unusual side effect of the move to 3D NAND was Continue reading “3D NAND’s Impact on the Equipment Market”

3D NAND: How do You Access the Control Gates?

(The following is an update of a post that originally ran on 8 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

One of the thornier problems Continue reading “3D NAND: How do You Access the Control Gates?”

An Alternative Kind of Vertical 3D NAND String

My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative Continue reading “An Alternative Kind of Vertical 3D NAND String”

3D NAND: Making a Vertical String

(The following is an update of a post that originally ran on 1 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

Let’s look at how one form of 3D NAND is manufactured. For this post we will explore Continue reading “3D NAND: Making a Vertical String”

What is a 3D NAND?

(The following is an update of a post that originally ran 25 October 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not Continue reading “What is a 3D NAND?”

Why Do We Need 3D NAND?

(The following is an update of a post that originally ran 18 October 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost Continue reading “Why Do We Need 3D NAND?”

Comparing Samsung V-NAND to Micron 16nm Planar NAND

I was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.

The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.

Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out. He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.

For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”

After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion. This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.

Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.

Samsung’s View on Charge Trap Flash

At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.

One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.

Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”

Samsung Announces 3D NAND Production

Samsung has announced production of its 3D NAND technology. This approach, first introduced by Toshiba in 2007, allows NAND flash makers to achieve more bits per chip by building NAND strings, which normally run across the surface of the chip, as vertical stacks.

It’s a fascinating technology, since it harnesses exotic steps invented by DRAM makers in the 1990s to get over scaling problems in that technology. At the time DRAM had to go vertical to follow Moore’s Law and there were two schools of vertical DRAM: Stacked Capacitor, and Trench Cell. The stacked capacitor camp layered polysilicon and silicon dioxide into layers to form a vertical capacitor. The trench camp etched a very narrow and deep hole into the silicon and lined it with the capacitor plates. Both worked very well, but over time the trench makers have Continue reading “Samsung Announces 3D NAND Production”