Everyone knows that flash memory is about to hit its scaling limit – it’s right around the corner. We’re ready for it because it’s been right around the corner for more than a decade now. It’s so close we can taste it.
When will it happen?
One thing that is quite clear is that nobody knows when NAND flash will stop scaling. Everyone knows that it’s soon, but researchers continue to find ways to push the technology another couple of process nodes past where anyone thought it could possibly go, and they have been doing this since Continue reading “The End of Flash Scaling”
Nostalgia buffs who lived through computing in the 1970s will enjoy some magnificent photos shared in a blog post by Ryszard Milewicz. These photos give three views of a ferrite core memory plane. The photo from this blog is a part of one of Mr. Milewicz’ close-up photos.
For those who were not exposed to core memory, this technology was based upon an approach in which every individual bit of a computer’s memory was a tiny donut made of compressed iron powder (“Ferrite”) that had to be hand strung with copper wire into a plane of bits.
A co-worker of The Memory Guy once had a high-speed core memory array that he used as Continue reading “Remembering Core Memory”
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading “IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?”
During this week’s International Solid State Circuits Conference (ISSCC) I learned some very valuable information about memories built using crosspoint matrices.
Since ISSCC is a conference at which you meet the best and brightest minds in the industry it should come as no surprise that I was able to meet with several of the most forward-thinking industry luminaries. One of them explained to me a very fundamental difficulty with resistive RAMs (ReRAMs): These devices require a forward current to be programmed to a “1” and a reverse current to be set to a zero. This goes against the ideal crosspoint memory design in which a bit would consist of nothing more than a diode in series with a memory element. By inserting a diode, the current can only run in one direction, so a bit can be programmed or it can be erased, but not both. This is called Continue reading “How Do You Make a ReRAM Work?”
A few articles at Computerworld, Tom’s Hardware, and The Verge were recently passed my way. These reported on a paper presented at last week’s USENIX conference that predicted how NAND flash’s future performance declines would impact tomorrow’s SSDs.
The paper found that SSD performance is likely to decrease over time as SSDs increase in capacity. The report postulates that SSDs of the future: “may be too slow and unreliable to be competitive against disks of similar cost in enterprise applications.”
Sadly, the Tom’s Hardware and Verge articles focused more on one of the assumptions behind the paper Continue reading “NAND SSD Performance to Decline over Time”
Rambus announced that the company has acquired privately-held Unity Semiconductor, an alternative memory technology company for $35 million. Unity employees have joined Rambus and will continue to develop next-generation nonvolatile memory.
Unity has an interesting technology that has caught the eye of some leading memory firms, including Micron, who had an exclusive right to Unity’s technology. The company’s CMOx is based on oxygen ions moving within a semiconducting material. It’s one species of resistive RAM.
Although Unity has been trying for years to manufacture very high density nonvolatile memory chips, The Memory Guy is not aware that the company has yet produced the chips they have set out to make.
Continue reading “Rambus Acquires Unity Semiconductor”
Elpida announced the development of a high-speed 64Mb non-volatile resistance memory (ReRAM) prototype using a 50nm process. The device was jointly developed with the New Energy and Industrial Technology Development Organization (NEDO), a Japanese-funded public institution.
Elpida will conduct further ReRAM development with Sharp Corporation, the National Institute of Advanced Industrial Science and Technology (AIST, another Japanese public institution) and the University of Tokyo.
It’s encouraging to see that Elpida still has its eye on projects into 2013 and beyond. The company is rumored to be working feverishly to find ways to stay in business through this year. Today’s DRAM market is a challenging one!
Continue reading “Elpida ReRAM Prototype”
At a Conference in San Francisco today (Tuesday December 13 ) ST-Ericsson and CEA-Leti presented a paper on something the companies called a: “Breakthrough 3DIC with Wide I/O Interface.”
This product appears to be a variation on the Hybrid Memory Cube, or HMC concept detailed in a prior post.
Remember that the HMC stacks a number of DRAM chips atop a logic chip. The memories store data and communicate to the logic chip through thousands of through-silicon vias (TSVs) while the logic chip handles communications with the outside world. Continue reading “WIOMING: Another Spin on the Hybrid Memory Cube”