Why Do We Need 3D NAND?

(The following is an update of a post that originally ran 18 October 2013.  It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)

A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost importance in the world of memory.

Memory chip makers have shrunk the cost of a bit some ten orders of magnitude since the 1960s largely by shrinking the lithographic process, or “scaling” to increasingly tighter process geometries.

Planar flash was always expected to reach a scaling limit. As flash approached the 15nm process node in 2010, technologists developed new processes and harnessed innovative materials to push scaling farther than it was expected to go.  In the end, though, everyone in the industry knew that there would come a point at which planar NAND could simply no longer be shrunk.

This had to do with the fact that the cells were squeezed so close to each other that the capacitive coupling between the two adjacent floating gates in the diagram below (pink orbs) became greater than the coupling from a cell’s own control gate to its floating gate (green circle).

To address this, the technology migrated from the standard floating gate to a capped structure (pictured below), to eliminate this undesirable capacitive coupling.

The capped cell solved the problem for a process generation or two, but capped cells can only be shrunk to about 20nm, since the thickness of the capping material’s sidewalls limited how closely floating gates could be placed to one another.

To get past this, some manufacturers replaced the silicon-based gate dielectric (aka blocking dielectric – the dielectric between the control gate and the floating gate) with a high-k material that allows the two gates to be placed closer to each other while still maintaining a high enough control gate coupling capacitance to do the trick.

Even that approach provided only a little more shrinkability. The industry wondered what would happen after that?

In 2007 a research team at Toshiba (now Kioxia) presented a novel idea to allow NAND chip densities to continue to scale. Rather than try to continue shrinking the cell’s length and width, why not turn the NAND string on its side?

The way this is done will be covered in the next post of this series.

This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was originally published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog.  In 2024 the series was updated in 2024 to honor the inventors of 3D NAND, who have received the 2024 FMS Lifetime Achievement Award.  The different sections are listed below, with a hot link to each section.

• Why Do We Need 3D NAND?
• What Is a 3D NAND?
• Making a Vertical NAND String
• An Alternative Kind of Vertical 3D NAND String
• How Do You Access the Control Gates?
• Benefits of Charge Traps over Floating Gates
• How Do You Erase and Program 3D NAND?
• 3D NAND’s Impact on the Equipment Market
• Who Will Make It and When?

Click on any of the above links to learn more about 3D NAND technology.