(The following is an update of a post that originally ran on 6 December 2013. It was republished in 2024 as a part of a series on The Memory Guy blog to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
A very unusual side effect of the move to 3D NAND was its impact on the equipment market. 3D NAND took the pressure off of lithographic steps to focus more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This was bad news for stepper makers like ASML, Canon, and Nikon while it was a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
Samsung explained at the technology’s introduction that the company would use 40nm lithography to produce NAND at an “effective process” of 10nm. This follows from the argument made in an earlier post that the process would be effectively shrunk by the square root of the number of layers. Samsung’s first product, the one it was discussing in that statement had only 16 layers of memory bits out of a total of 24 total layers, with the other layers serving as select gates and such.
Semiconductor makers try their best to re-use process equipment as much as possible when they switch from one generation to the next. This helps them control CapEx (capital expense) costs. Because all of the equipment was being changed for 3D NAND, the move to 3D was significantly more costly than prior flash generation updates, since a significant investment had to be made in deposition and etch equipment to keep the converted fab running at its peak capacity. Some lithography tools were decommissioned from these fabs since they were no longer needed.
The graphic below, a slide presented in 2012 by Applied Materials, compares the incremental lithography and other investments required to migrate to a couple of generations of planar NAND flash (3X, 1X, & 1Y, referring to the process in nanometers) and to the first generation of 3D NAND.
The blue chart on the left of this graphic shows the incremental lithography investment, and the green charts to its right show tool investments for thermal processes (annealing) and ion implant, chemical vapor deposition (CVD), and plasma etch. It’s pretty clear that the green graphs on the right are increasing from one generation to the next, while the blue chart on the left is decreasing. Applied Materials compiled this chart to tell us that lithography spending would decrease while other processing equipment expenditures would increase, at least for NAND flash.
At that time, though, ASML, the leading lithography tool maker, presented a very different viewpoint on this matter, which the company illustrated with the next chart. This chart doesn’t represent any single process, rather it is based on the average of the company’s customers and the average of their process geometries.
The chart’s horizontal axis shows three different processes and their years of mass production: 2x 2D is a planar (2D) process in the 20-29nm range. 1x 2d is a planar process smaller than 20nm, and 5x-24 3D represents a 3D NAND with 24 layers produced using 5Xnm lithography.
The vertical axis shows the number of lithography passes: how many times must the wafer be exposed by a certain type of scanner? (Keep in mind that these numbers are a combination of typical numbers for the average vendor, and don’t represent any particular vendor’s process.)
Each column is broken down to show the tool type that is required. The bottom dark gray is the i-Line tool, the oldest and least expensive scanner in a typical NAND flash fab. These are generally used for the peripheral CMOS circuitry which can be produced using larger features than the memory bits themselves. The number of passes over these tools changes very little from process to process. The medium-gray portion represents the Kr-F (Krypton-Fluorine) scanner, which is also relatively inexpensive and its use also increases slightly from process to process. The lightest gray section is a more costly ArF (Argon-Fluorine) stepper, which is used, on average, for two passes for any of these processes. At the top is the blue portion of the column, representing immersion ArF lithography tools, the costliest scanner in the fab, which is reserved for critical mask layers. The ArF tool is used for only seven process steps in both the 2Xnm and 1Xnm process, but this number jumps to ten steps for 3D.
ASML told me that some of these critical steps are unique to 3D NAND, like making the hole, cutting the slits, and etching the vias to the stairsteps.
The third graphic is a chart that SanDisk (now Western Digital) shared during an analyst meeting in 2013. The turquoise columns illustrate the per-wafer cost of tooling a brand new fab for each process node. The shorter maroon columns represent the per-wafer cost to convert a fab from the prior generation to the current process generation.
According to SanDisk, each upcoming transition, starting with 19nm (the company’s “1X” technology) would be more costly than prior generations, since so many new tools would need to be purchased, tools that were not required for any of the company’s prior flash generations. The migration from SanDisk’s 1X (19x26nm) to its 1Y (19×19.5nm) process required the addition of a Hi-k gate dielectric. At that time, neither Toshiba (now Kioxia) nor SanDisk/WDC had disclosed the process these companies planned to use for their 1Z transition, but the chart indicates that this transition would be more costly than preceding transitions. It’s safe to assume that migration to 3D would require an even larger complement of new materials tools at a significant increase in cost. SanDisk presented this to the investment community to warn of its negative upcoming impact on the company’s profits.
Now you have three versions of the story: A deposition/etch tool maker’s, a lithography tool maker’s, and a NAND flash maker’s. I am sure that a little bit of each one actually came to pass, but that’s not something that these companies are likely to reveal to me!
Another concern voiced by NAND makers in 2013 was whether they would be able to shrink 3D NAND’s features to continue to reduce costs. After all, process shrinks were the most significant way they reduced costs when they were making planar NAND, with the second being MLC. Shrinks were something they understood well. Plus, at that time few NAND makers could envision 3D NAND with more than 48 layers. Let’s see what they were considering for further cost reductions.
Shrinking 3D NAND Feature Sizes
When this post was originally published, it wasn’t yet clear whether 3D NAND makers could use lithography to tighten up the layout of 3D NAND. It ended up that 3D NAND columns can’t be placed much closer to each other than they originally were. The limitation to any column’s width has a lot to do with how thinly the sidewalls can be deposited onto the sides of the hole, and how extreme of an aspect ratio can be etched into the stacked layers. One additional challenge is that shrinking the width of the column would make the NAND string have a thinner channel, limiting current to the point that the cells on the string could no longer work.
Early in 3D NAND’s lifetime Toshiba pointed out that its original BiCS columns could be made thinner than Samsung’s TCAT, but other issues motivated Toshiba to convert to a process like Samsung’s. Likewise, Micron dropped the floating gate approach that it had developed with Intel, leaving Intel’s flash division, now known as Solidigm, as the only company to remain with that process.
The aspect ratio problem has been addressed in varying degrees by making the layers thinner, with some companies, particularly Samsung, focusing intensely on layer thickness, while others used string stacking to make multiple “Decks” with lower aspect ratio holes.
Shrinking the layers causes other difficulties: You can only shrink these layers by a limited amount in a practical production environment, so that’s one issue. Then there’s an additional problem because the thickness of the conductive polysilicon or tantalum layer defines gate length in the string: The thinner the layer, the shorter the gate. A third issue is that thinning the conductive layer also increases its resistance, causing other issues.
But there are insulating layers between the conductive wordline layers. Perhaps those can be shrunk instead. Actually, making the insulating layers thinner can also lead to issues since these layers need to isolate the wordlines from each other. As the insulating layer is thinned the capacitive coupling between wordlines increases, leading to crosstalk and disturb issues, and lower speed operation.
Another cost-related issue was that NAND flash could no longer move into an obsolete DRAM fab (or vice-versa) to realize savings by using the same equipment twice. That worked well for planar NAND, but 3D NAND eliminated that possibility.
DRAM ≠ NAND
One interesting side effect of the transition to 3D NAND was that DRAM and NAND wafer fabrication plants (“fabs”) diverged significantly from each other. Most NAND makers (with the exception of Kioxia, WDC, and YMTC) also make DRAM chips. With planar NAND, these NAND/DRAM manufacturers could build a new fab but wait until the last minute to decide whether to to manufacture NAND flash or DRAM in that new fab. A decade earlier, some even tried to make fully-fungible fabs that could switch rapidly and frequently between NAND and DRAM production. These manufacturers found that the equipment balances of these two technologies were too different from each other, resulting in idle equipment. The depreciation of this idle equipment would still be counted against costs, increasing the cost structure of the fab, and since both NAND and DRAM are highly cost sensitive this approach was abandoned.
3D NAND fabs are tooled for a large number of deposition and etch steps, and few lithography steps, whereas DRAM fabs’ tooling costs continue to be dominated by lithography, so there are fewer commonalities between DRAM and 3D NAND fab tooling than there were with DRAM and planar NAND. Very few manufacturers today would even consider converting a fab from one technology to the other.
This brings us to the question: “Who the manufacturers 3D NAND?” which is the topic of the next (and final) post of this series.
This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was originally published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog and was updated in 2024. The different sections are listed below, with a hot link to each section.
- Why Do We Need 3D NAND?
- What Is a 3D NAND?
- Making a Vertical NAND String
- An Alternative Kind of Vertical 3D NAND String
- How Do You Access the Control Gates?
- Benefits of Charge Traps over Floating Gates
- How Do You Erase and Program 3D NAND?
- 3D NAND’s Impact on the Equipment Market
- Who Will Make It and When?
Click on any of the above links to learn more about 3D NAND technology.
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