(The following is an update of a post that originally ran on 29 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?”
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This is a concept first introduced in a NAND EPROM presented by RCA in 1986!
NAND’s program/erase differs from NOR flash which programs bits using Channel Hot Electron Injection (CHE, also known as Hot-Carrier Injection) and FN for erase. It also differs from the MirrorBit Charge Trapping NOR Flash introduced by Spansion (now Infineon) which uses yet another erase mechanism called Hot Hole Injection. We won’t be going into either of these mechanisms in this post.
Fowler-Nordheim tunneling is used in planar as well as 3D NAND to both add and remove the charge to perform program and erase. The graphic below helps to illustrate how FN tunneling works.
FN tunneling is something of a brute force approach: a high enough voltage is placed between the control gate and the channel’s source and drain to force a current to attempt to flow from the channel through the floating gate to the control gate. This current either brings electrons from the channel onto the floating gate to program the cell, or, if it’s reversed, it drags electrons out of the floating gate back to the channel to erase that cell.
Why are different methods used for NAND as for NOR? CHE can program a cell two orders of magnitude faster than FN, but it takes a 4-5 orders of magnitude more power to do the programming. NOR flash can use CHE since it programs one byte at a time, but NAND flash is programmed a page at a time, and each page consists of 8K bytes or more, or over 65,000 bits, which would cause a massive power surge during programming. This makes FN a better option for NAND flash, even though it is significantly slower process. The internal parallelism of NAND flash helps to offset the fact that FN is slow.
There is an interesting difference between the erase mechanism in TCAT and that of BiCS. The TCAT cell uses the same kind of connections as a planar NAND, so electrons are tunneled from the floating gate back into the channel when a negative bias is applied to the control gate and a positive bias to the channel. BiCS doesn’t actually route a current to the channel, but instead uses a phenomenon called GIDL (Gate-Induced Drain Leakage) to create holes in the un-connected channel by placing a positive voltage on the control gate. The control gate voltage is then switched negative, attracting the holes into the charge trap where they recombine with the trapped electrons to remove the charge. It’s still FN, but it’s a different way to set the current up.
Other aspects of the 3D NAND are fundamentally the same as they are in planar NAND. Reading and programming are performed in pages and erasure is done in blocks, although the sizes of these pages and blocks differ between planar and 3D NAND according to the length of the strings or the number of layers in the vertical structure.
From the user’s standpoint there are minor differences between how a system or controller chip interfaces with planar and 3D NAND. The programming details above are handled internally to the chip, so external commands used for read, program, and erase are very similar, if not identical, between planar and 3D NAND flash.
One interesting difference is that 3D NAND program and erase times are faster than those of planar NAND, and the current consumed during program and erase is lower, thanks to 3D NAND’s use of a charge trapping layer. This gives engineers more flexibility than they had with floating gate planar NAND flash, simplifying their jobs a bit. Endurance has improved as well, since charge trap flash, with its lower programming voltage, puts less stress on the tunnel oxide than a floating gate process.
3D NAND does introduce new error and noise issues that didn’t exist with planar NAND. Unique noise modes, read and write disturb, and other error-producing mechanisms have been found, but these are problems that designers understand how to manage.
This post is a part of a series called What is 3D NAND? Why do we need it? How do they make it? that was originally published in weekly segments during the fourth quarter of 2013 on The Memory Guy blog and was updated in 2024. The different sections are listed below, with a hot link to each section.
- Why Do We Need 3D NAND?
- What Is a 3D NAND?
- Making a Vertical NAND String
- An Alternative Kind of Vertical 3D NAND String
- How Do You Access the Control Gates?
- Benefits of Charge Traps over Floating Gates
- How Do You Erase and Program 3D NAND?
- 3D NAND’s Impact on the Equipment Market
- Who Will Make It and When?
Click on any of the above links to learn more about 3D NAND technology.
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